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Micrel, Inc.
Programming
General
The MICRF600 functions are enabled through a number of
programming bits. The programming bits are organized as
a set of addressable control registers, each register
holding 8 bits.
There are 23 control registers in total in the MICRF600,
and they have addresses ranging from 0 to 22. The user
can read all the control registers. The user can write to the
first 22 registers (0 to 21); the register 22 is a read-only
register.
All control registers hold 8 bits and all 8 bits must be
written to when accessing a control register, or they will be
read. Some of the registers do not utilize all 8 bits. The
value of an unused bit is “don’t care.”
The control register with address 0 is referred to as
ControlRegister0, the control register with address 1 is
ControlRegister1 and so on. A summary of the control
registers is given in the table below. In addition to the
unused bits (marked with”-“) there are a number of fixed
bits (marked with “0” or “1”). Always maintain these as
Address
MICRF600/MICRF600Z
shown in the table.
The control registers in MICRF600 are accessed through a
3-wire interface; clock, data and chip select. These lines
are referred to as SCLK, IO, and CS, respectively. This 3-
wire interface is dedicated to control register access and is
referred to as the control interface. Received data (via RF)
and data to transmit (via RF) are handled by the DataIXO
and DataClk (if enabled) lines; this is referred to as the
data interface.
The SCLK line is applied externally; access to the control
registers are carried out at a rate determined by the user.
The MICRF600 will ignore transitions on the SCLK line if
the CS line is inactive. The MICRF600 can be put on a
bus, sharing clock and data lines with other devices.
All control registers should be written to after a battery
reset. During operation, it is sufficient to write to one
register only. The MICRF600 will automatically enter
power down mode after a battery reset.
Data
A6…A0
0000000
0000001
0000010
0000011
0000100
0000101
D7
LNA_by
‘1’
‘0’
‘1’
‘0’
-
D6
PA2
‘0’
‘SC_by’
‘1’
‘0’
-
D5
PA1
‘0’
‘0’
‘0’
‘0’
‘0’
D4
PA0
‘0’
‘PA_by’
VCO_IB2
‘0’
‘1’
D3
Sync_en
RSSI_en
‘0’
VCO_IB1
‘0’
‘0’
D2
Mode1
LD_en
‘0’
VCO_IB0
‘0’
‘0’
D1
Mode0
PF_FC1
‘0’
VCO_freq1
‘0’
‘0’
D0
‘1’
PF_FC0
‘0’
VCO_freq0
‘0’
‘0’
0000110
-
‘0’
‘0’
‘0’
BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2
0000111 BitRate_clkS1BitRate_clkS0 RefClk_K5 RefClk_K4
RefClk_K3
RefClk_K2
RefClk_K1
RefClk_K0
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
‘1’
‘0’
-
-
N0_7
-
M0_7
-
-
N1_7
-
M1_7
‘1’
-
FEE_7
‘1’
‘0’
-
-
N0_6
-
M0_6
-
-
N1_6
-
M1_6
‘0’
-
FEE_6
ScClk5
‘1’
A0_5
-
N0_5
-
M0_5
A1_5
-
N1_5
-
M1_5
‘1’
-
FEE_5
ScClk4
XCOtune4
A0_4
-
N0_4
-
M0_4
A1_4
-
N1_4
-
M1_4
‘1’
-
FEE_4
ScClk3
XCOtune3
A0_3
N0_11
N0_3
M0_11
M0_3
A1_3
N1_11
N1_3
M1_11
M1_3
‘0’
FEEC_3
FEE_3
ScClk2
XCOtune2
A0_2
N0_10
N0_2
M0_10
M0_2
A1_2
N1_10
N1_2
M1_10
M1_2
‘1’
FEEC_2
FEE_2
ScClk1
XCOtune1
A0_1
N0_9
N0_1
M0_9
M0_1
A1_1
N1_9
N1_1
M1_9
M1_1
‘0’
FEEC_1
FEE_1
ScClk0
XCOtune0
A0_0
N0_8
N0_0
M0_8
M0_0
A1_0
N1_8
N1_0
M1_8
M1_0
‘1’
FEEC_0
FEE_0
Table 1. Control Registers in MICRF600
July 2006
7
M9999-082505
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